Home
last modified time | relevance | path

Searched refs:RISCV_IOMMU_MSI_PTE_V (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h404 #define RISCV_IOMMU_MSI_PTE_V BIT_ULL(0) macro
H A Driscv-iommu.c573 if (!(pte[0] & RISCV_IOMMU_MSI_PTE_V) || (pte[0] & RISCV_IOMMU_MSI_PTE_C)) { in riscv_iommu_msi_write()