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Searched refs:RISCV_IOMMU_IPSR_FIP (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h177 #define RISCV_IOMMU_IPSR_FIP BIT(1) macro
H A Driscv-iommu.c1873 if (data & RISCV_IOMMU_IPSR_FIP) { in riscv_iommu_update_ipsr()
1879 ipsr_set |= RISCV_IOMMU_IPSR_FIP; in riscv_iommu_update_ipsr()
1881 ipsr_clr |= RISCV_IOMMU_IPSR_FIP; in riscv_iommu_update_ipsr()
1884 ipsr_clr |= RISCV_IOMMU_IPSR_FIP; in riscv_iommu_update_ipsr()