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Searched refs:RISCV_IOMMU_FQ_HDR_CAUSE (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h33 #define RISCV_IOMMU_FQ_HDR_CAUSE GENMASK_ULL(11, 0) macro
H A Driscv-iommu.c519 ev.hdr = set_field(ev.hdr, RISCV_IOMMU_FQ_HDR_CAUSE, cause); in riscv_iommu_report_fault()