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Searched refs:RISCV_IOMMU_FQ_CAUSE_MSI_INVALID (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h338 RISCV_IOMMU_FQ_CAUSE_MSI_INVALID = 262, enumerator
H A Driscv-iommu.c581 cause = RISCV_IOMMU_FQ_CAUSE_MSI_INVALID; in riscv_iommu_msi_write()