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Searched refs:RISCV_IOMMU_FQCSR_FQON (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/tests/qtest/libqos/
H A Driscv-iommu.h54 #define RISCV_IOMMU_FQCSR_FQON RISCV_IOMMU_QUEUE_ACTIVE macro
/openbmc/qemu/tests/qtest/
H A Driscv-iommu-test.c73 g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FQON, ==, 0); in test_reg_reset()
/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h162 #define RISCV_IOMMU_FQCSR_FQON RISCV_IOMMU_QUEUE_ACTIVE macro
H A Driscv-iommu.c126 if (!(ctrl & RISCV_IOMMU_FQCSR_FQON) || in riscv_iommu_fault()
1730 bool active = !!(ctrl_set & RISCV_IOMMU_FQCSR_FQON); in riscv_iommu_process_fq_control()
1739 ctrl_set = RISCV_IOMMU_FQCSR_FQON; in riscv_iommu_process_fq_control()
1745 ctrl_clr = RISCV_IOMMU_FQCSR_BUSY | RISCV_IOMMU_FQCSR_FQON; in riscv_iommu_process_fq_control()
2185 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_FQCSR], RISCV_IOMMU_FQCSR_FQON | in riscv_iommu_realize()