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Searched refs:RISCV_IOMMU_FQCSR_FQMF (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h160 #define RISCV_IOMMU_FQCSR_FQMF RISCV_IOMMU_QUEUE_MEM_FAULT macro
H A Driscv-iommu.c127 !!(ctrl & (RISCV_IOMMU_FQCSR_FQOF | RISCV_IOMMU_FQCSR_FQMF))) { in riscv_iommu_fault()
139 RISCV_IOMMU_FQCSR_FQMF, 0); in riscv_iommu_fault()
1740 ctrl_clr = RISCV_IOMMU_FQCSR_BUSY | RISCV_IOMMU_FQCSR_FQMF | in riscv_iommu_process_fq_control()
1878 fqcsr & RISCV_IOMMU_FQCSR_FQMF)) { in riscv_iommu_update_ipsr()
2183 stl_le_p(&s->regs_wc[RISCV_IOMMU_REG_FQCSR], RISCV_IOMMU_FQCSR_FQMF | in riscv_iommu_realize()