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Searched refs:RISCV_IOMMU_DC_TC_V (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu.c880 ctx->tc = RISCV_IOMMU_DC_TC_V; in riscv_iommu_ctx_fetch()
964 if (!(ctx->tc & RISCV_IOMMU_DC_TC_V)) { in riscv_iommu_ctx_fetch()
1074 if (ctx->tc & RISCV_IOMMU_DC_TC_V && in riscv_iommu_ctx_inval_devid_procid()
1077 ctx->tc &= ~RISCV_IOMMU_DC_TC_V; in riscv_iommu_ctx_inval_devid_procid()
1086 if (ctx->tc & RISCV_IOMMU_DC_TC_V && in riscv_iommu_ctx_inval_devid()
1088 ctx->tc &= ~RISCV_IOMMU_DC_TC_V; in riscv_iommu_ctx_inval_devid()
1096 if (ctx->tc & RISCV_IOMMU_DC_TC_V) { in riscv_iommu_ctx_inval_all()
1097 ctx->tc &= ~RISCV_IOMMU_DC_TC_V; in riscv_iommu_ctx_inval_all()
1129 if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) { in riscv_iommu_ctx()
H A Driscv-iommu-bits.h232 #define RISCV_IOMMU_DC_TC_V BIT_ULL(0) macro