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Searched refs:RISCV_IOMMU_DC_TC_SADE (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h240 #define RISCV_IOMMU_DC_TC_SADE BIT_ULL(8) macro
H A Driscv-iommu.c391 ctx->tc & (pass ? RISCV_IOMMU_DC_TC_GADE : RISCV_IOMMU_DC_TC_SADE); in riscv_iommu_spa_fetch()