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Searched refs:RISCV_IOMMU_CQCSR_CQEN (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/tests/qtest/
H A Driscv-iommu-test.c65 g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CQEN, ==, 0); in test_reg_reset()
154 reg |= RISCV_IOMMU_CQCSR_CQEN; in test_iommu_init_queues()
/openbmc/qemu/tests/qtest/libqos/
H A Driscv-iommu.h46 #define RISCV_IOMMU_CQCSR_CQEN RISCV_IOMMU_QUEUE_ENABLE macro
/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h147 #define RISCV_IOMMU_CQCSR_CQEN RISCV_IOMMU_QUEUE_ENABLE macro
H A Driscv-iommu.c1698 bool enable = !!(ctrl_set & RISCV_IOMMU_CQCSR_CQEN); in riscv_iommu_process_cq_control()