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Searched refs:RISCV_IOMMU_CQCSR_CMD_ILL (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h151 #define RISCV_IOMMU_CQCSR_CMD_ILL BIT(10) macro
H A Driscv-iommu.c1553 !!(ctrl & (RISCV_IOMMU_CQCSR_CMD_ILL | RISCV_IOMMU_CQCSR_CQMF))) { in riscv_iommu_process_cq_tail()
1677 RISCV_IOMMU_CQCSR_CMD_ILL, 0); in riscv_iommu_process_cq_tail()
1710 RISCV_IOMMU_CQCSR_CMD_ILL | RISCV_IOMMU_CQCSR_CMD_TO | in riscv_iommu_process_cq_control()
1862 cqcsr & RISCV_IOMMU_CQCSR_CMD_ILL || in riscv_iommu_update_ipsr()
2180 RISCV_IOMMU_CQCSR_CMD_TO | RISCV_IOMMU_CQCSR_CMD_ILL); in riscv_iommu_realize()