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Searched refs:RISCV_IOMMU_CAP_SV48 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h74 #define RISCV_IOMMU_CAP_SV48 BIT_ULL(10) macro
H A Driscv-iommu.c353 sv_mode = pass ? RISCV_IOMMU_CAP_SV48X4 : RISCV_IOMMU_CAP_SV48; in riscv_iommu_spa_fetch()
768 if (!(s->cap & RISCV_IOMMU_CAP_SV48)) { in riscv_iommu_validate_device_ctx()
835 if (!(s->cap & RISCV_IOMMU_CAP_SV48)) { in riscv_iommu_validate_process_ctx()
2129 RISCV_IOMMU_CAP_SV48 | RISCV_IOMMU_CAP_SV57; in riscv_iommu_realize()