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Searched refs:RISCV_IOMMU_CAP_SV32 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h72 #define RISCV_IOMMU_CAP_SV32 BIT_ULL(8) macro
H A Driscv-iommu.c324 sv_mode = pass ? RISCV_IOMMU_CAP_SV32X4 : RISCV_IOMMU_CAP_SV32; in riscv_iommu_spa_fetch()
756 if (fsc_mode == RISCV_IOMMU_CAP_SV32 && in riscv_iommu_validate_device_ctx()
757 !(s->cap & RISCV_IOMMU_CAP_SV32)) { in riscv_iommu_validate_device_ctx()
824 !(s->cap & RISCV_IOMMU_CAP_SV32)) { in riscv_iommu_validate_process_ctx()
2128 s->cap |= RISCV_IOMMU_CAP_SV32 | RISCV_IOMMU_CAP_SV39 | in riscv_iommu_realize()