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Searched refs:RISCV_EXCP_SW_CHECK (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzicfiss.c.inc45 tcg_constant_i32(RISCV_EXCP_SW_CHECK));
H A Dtrans_rvi.c.inc59 tcg_constant_i32(RISCV_EXCP_SW_CHECK));
72 tcg_constant_i32(RISCV_EXCP_SW_CHECK));
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h779 RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */ enumerator
H A Dtranslate.c1379 tcg_constant_i32(RISCV_EXCP_SW_CHECK)); in riscv_tr_translate_insn()
H A Dcpu_helper.c2257 case RISCV_EXCP_SW_CHECK: in riscv_cpu_do_interrupt()
H A Dcsr.c1794 (1ULL << (RISCV_EXCP_SW_CHECK)) | \