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Searched refs:RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h11523 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 macro
H A Ddce_10_0_sh_mask.h12625 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 macro
H A Ddce_11_0_sh_mask.h12631 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 macro
H A Ddce_11_2_sh_mask.h13247 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 macro
H A Ddce_12_0_sh_mask.h56101 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h27130 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK … macro
H A Ddcn_1_0_sh_mask.h974 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK … macro
H A Ddcn_3_0_1_sh_mask.h242 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK … macro
H A Ddcn_3_2_1_sh_mask.h47870 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK … macro
H A Ddcn_3_1_5_sh_mask.h51065 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK … macro
H A Ddcn_3_0_2_sh_mask.h54177 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK … macro
H A Ddcn_2_0_0_sh_mask.h59173 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK … macro
H A Ddcn_3_0_0_sh_mask.h62755 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK … macro
H A Ddcn_3_2_0_sh_mask.h47872 #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK … macro