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Searched refs:RIRB_CONTROL__RIRB_DMA_ENABLE_MASK (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h11513 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 macro
H A Ddce_10_0_sh_mask.h12615 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 macro
H A Ddce_11_0_sh_mask.h12621 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 macro
H A Ddce_11_2_sh_mask.h13237 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 macro
H A Ddce_12_0_sh_mask.h56090 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h27119 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK … macro
H A Ddcn_1_0_sh_mask.h963 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK … macro
H A Ddcn_3_0_1_sh_mask.h231 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK … macro
H A Ddcn_3_2_1_sh_mask.h47859 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK … macro
H A Ddcn_3_1_5_sh_mask.h51057 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK … macro
H A Ddcn_3_0_2_sh_mask.h54166 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK … macro
H A Ddcn_2_0_0_sh_mask.h59162 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK … macro
H A Ddcn_3_0_0_sh_mask.h62744 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK … macro
H A Ddcn_3_2_0_sh_mask.h47861 #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK … macro