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Searched refs:RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h11512 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 macro
H A Ddce_10_0_sh_mask.h12614 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 macro
H A Ddce_11_0_sh_mask.h12620 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 macro
H A Ddce_11_2_sh_mask.h13236 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 macro
H A Ddce_12_0_sh_mask.h56086 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h27115 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT … macro
H A Ddcn_1_0_sh_mask.h959 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h227 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h47855 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h54162 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h59158 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h62740 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h47857 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT … macro