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Searched refs:RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h11511 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 macro
H A Ddce_10_0_sh_mask.h12613 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 macro
H A Ddce_11_0_sh_mask.h12619 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 macro
H A Ddce_11_2_sh_mask.h13235 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 macro
H A Ddce_12_0_sh_mask.h56089 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h27118 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
H A Ddcn_1_0_sh_mask.h962 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
H A Ddcn_3_0_1_sh_mask.h230 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
H A Ddcn_3_2_1_sh_mask.h47858 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
H A Ddcn_3_0_2_sh_mask.h54165 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
H A Ddcn_2_0_0_sh_mask.h59161 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
H A Ddcn_3_0_0_sh_mask.h62743 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro
H A Ddcn_3_2_0_sh_mask.h47860 #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … macro