Searched refs:RG_HDMITXPLL_PWD (Results 1 – 2 of 2) sorted by relevance
102 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); in mtk_hdmi_pll_set_hw()386 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); in mtk_hdmi_pll_prepare()401 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); in mtk_hdmi_pll_unprepare()
89 #define RG_HDMITXPLL_PWD BIT(31) macro