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Searched refs:RESET (Results 1 – 25 of 60) sorted by relevance

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/openbmc/u-boot/drivers/clk/sunxi/
H A Dclk_r40.c57 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
58 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
59 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
61 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
62 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
63 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
64 [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
65 [RST_BUS_GMAC] = RESET(0x2c0, BIT(17)),
66 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
67 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[all …]
H A Dclk_h3.c53 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
54 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
55 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
56 [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
58 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
59 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
60 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
61 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
62 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
63 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[all …]
H A Dclk_a31.c53 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
54 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
55 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
57 [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
58 [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
59 [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
60 [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
61 [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)),
62 [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
63 [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
[all …]
H A Dclk_a64.c46 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
47 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
48 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
50 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
51 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
52 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
53 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
54 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
55 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
56 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
[all …]
H A Dclk_a83t.c44 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
45 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
46 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
48 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
49 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
50 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
51 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
52 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
53 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
54 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[all …]
H A Dclk_a23.c42 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
43 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
44 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
46 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
47 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
48 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
49 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
50 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
51 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
52 [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
[all …]
H A Dclk_h6.c34 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
35 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
36 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
37 [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
38 [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
39 [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
40 [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
42 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
43 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
45 [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
H A Dclk_v3s.c32 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
34 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
35 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
36 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
37 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
38 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
40 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
41 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
42 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
H A Dclk_a80.c36 [RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
37 [RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
38 [RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
39 [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
40 [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
42 [RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
43 [RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
44 [RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
45 [RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
46 [RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
[all …]
H A Dclk_a10.c54 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
55 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
56 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
H A Dclk_a10s.c42 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
43 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dsec_boot.S88 .word 0x1 @ CPU0_STATE : RESET
89 .word 0x2 @ CPU1_STATE : SECONDARY RESET
90 .word 0x2 @ CPU2_STATE : SECONDARY RESET
91 .word 0x2 @ CPU3_STATE : SECONDARY RESET
/openbmc/qemu/docs/spin/
H A Dwin32-qemu-event.promela26 #define RESET RAW_RESET
31 * primitives. SET/RESET/WAIT have exactly the same semantics as
52 #define RESET if :: state == EV_SET -> atomic { state = state | EV_FREE; } \
84 RESET;
/openbmc/u-boot/tools/patman/
H A Dterminal.py99 RESET = '\033[0m' variable in Color
138 return self.RESET
161 return start + text + self.RESET
/openbmc/u-boot/drivers/fpga/
H A Divm_core.c251 { RESET, RESET, 0xFC, 6 }, /* Transitions from RESET */
252 { RESET, IDLE, 0x00, 1 },
253 { RESET, DRPAUSE, 0x50, 5 },
254 { RESET, IRPAUSE, 0x68, 6 },
255 { IDLE, RESET, 0xE0, 3 }, /* Transitions from IDLE */
258 { DRPAUSE, RESET, 0xF8, 5 }, /* Transitions from DRPAUSE */
262 { IRPAUSE, RESET, 0xF8, 5 }, /* Transitions from IRPAUSE */
333 case RESET: in GetState()
2441 (cNextJTAGState != RESET)) { in ispVMStateMachine()
2496 ispVMStateMachine(RESET); /*step devices to RESET state*/ in ispVMStart()
[all …]
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/
H A Du-boot-fvp-base.inc5 file://0002-vexpress64-Select-PSCI-RESET-by-default.patch \
/openbmc/u-boot/drivers/rtc/
H A Dds1302.c18 #define RESET rtc_go_low(RST), rtc_go_low(SCLK) macro
164 RESET; in read_ser_drv()
184 RESET; in write_ser_drv()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dccu.h51 #define RESET(_off, _bit) { \ macro
/openbmc/u-boot/board/freescale/mx28evk/
H A DREADME20 * JTAG PSWITCH RESET: To the right (reset disabled)
29 * JTAG PSWITCH RESET: To the right (reset disabled)
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/mycroft/files/
H A D0003-dev_setup.sh-Remove-the-TERM-dependency.patch27 - RESET=$(tput sgr0)
H A D0004-dev_setup.sh-Ignore-missing-package-manager.patch18 …libffi libjpg openssl autoconf bison swig glib2.0 portaudio19 mpg123 flac curl fann g++ jq\n$RESET"
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base/
H A D0002-vexpress64-Select-PSCI-RESET-by-default.patch4 Subject: [PATCH] vexpress64: Select PSCI RESET by default
/openbmc/u-boot/board/rockchip/evb_rv1108/
H A DREADME17 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
/openbmc/u-boot/board/rockchip/evb_rk3399/
H A DREADME112 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
120 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
/openbmc/u-boot/board/rockchip/sheep_rk3368/
H A DREADME23 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:

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