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Searched refs:REG_TRAINING_WL_UPD_OFFS (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp.h316 #define REG_TRAINING_WL_UPD_OFFS 2 macro
H A Dddr3_write_leveling.c1179 reg |= (1 << REG_TRAINING_WL_UPD_OFFS); /* [2] - trnWLCsUpd */ in ddr3_write_leveling_single_cs()