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Searched refs:REG_TRAINING_WL_2TO1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp.h320 #define REG_TRAINING_WL_2TO1 0x10 macro
H A Dddr3_write_leveling.c1196 REG_TRAINING_WL_RATIO_MASK) | REG_TRAINING_WL_2TO1; in ddr3_write_leveling_single_cs()
1243 REG_TRAINING_WL_2TO1; in ddr3_write_leveling_single_cs()