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Searched refs:REG_SET_FLD_NUM (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/accel/ivpu/
H A Divpu_hw_40xx.c172 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val); in ivpu_pll_cmd_send()
173 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val); in ivpu_pll_cmd_send()
177 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val); in ivpu_pll_cmd_send()
178 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, epp, val); in ivpu_pll_cmd_send()
182 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val); in ivpu_pll_cmd_send()
183 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, CDYN, cdyn, val); in ivpu_pll_cmd_send()
H A Divpu_hw_37xx.c154 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val); in ivpu_pll_cmd_send()
155 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val); in ivpu_pll_cmd_send()
159 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val); in ivpu_pll_cmd_send()
160 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, PLL_DEFAULT_EPP_VALUE, val); in ivpu_pll_cmd_send()
164 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val); in ivpu_pll_cmd_send()
H A Divpu_hw_reg_io.h43 #define REG_SET_FLD_NUM(REG, FLD, num, val) \ macro