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Searched refs:REG_SET_FLD (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/accel/ivpu/
H A Divpu_hw_37xx.c168 val = REG_SET_FLD(VPU_37XX_BUTTRESS_WP_REQ_CMD, SEND, val); in ivpu_pll_cmd_send()
286 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val); in ivpu_boot_host_ss_rst_clr_assert()
287 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val); in ivpu_boot_host_ss_rst_clr_assert()
288 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val); in ivpu_boot_host_ss_rst_clr_assert()
298 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); in ivpu_boot_host_ss_rst_drive()
299 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
300 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
315 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); in ivpu_boot_host_ss_clk_drive()
316 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
317 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
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H A Divpu_hw_40xx.c187 val = REG_SET_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, val); in ivpu_pll_cmd_send()
273 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); in ivpu_boot_host_ss_rst_drive()
274 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
275 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
290 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); in ivpu_boot_host_ss_clk_drive()
291 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
292 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
370 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in ivpu_boot_idle_gen_drive()
444 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
667 val = REG_SET_FLD(VPU_40XX_BUTTRESS_D0I3_CONTROL, I3, val); in ivpu_boot_d0i3_drive()
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H A Divpu_hw_reg_io.h41 #define REG_SET_FLD(REG, FLD, val) \ macro