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Searched refs:REG_SET_BIT (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c288 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, in ar9002_olc_init()
488 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9002_hw_spectral_scan_config()
489 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9002_hw_spectral_scan_config()
497 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit); in ar9002_hw_spectral_scan_config()
522 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
536 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9002_hw_spectral_scan_trigger()
538 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_trigger()
557 REG_SET_BIT(ah, 0x9864, 0x7f000); in ar9002_hw_tx99_start()
558 REG_SET_BIT(ah, 0x9924, 0x7f00fe); in ar9002_hw_tx99_start()
567 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ar9002_hw_tx99_start()
[all …]
H A Dar9003_wow.c34 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_sta_powersave()
133 REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count)); in ath9k_hw_wow_apply_pattern()
135 REG_SET_BIT(ah, AR_MAC_PCU_WOW4, BIT(pattern_count - 8)); in ath9k_hw_wow_apply_pattern()
312 REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PMCTRL_HOST_PME_EN | in ath9k_hw_wow_enable()
326 REG_SET_BIT(ah, AR_WOW_PATTERN, in ath9k_hw_wow_enable()
332 REG_SET_BIT(ah, AR_WOW_COUNT, AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) | in ath9k_hw_wow_enable()
387 REG_SET_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN); in ath9k_hw_wow_enable()
441 REG_SET_BIT(ah, AR_PCIE_PHY_REG3, BIT(13)); in ath9k_hw_wow_enable()
H A Dar9002_calib.c75 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
265 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
458 REG_SET_BIT(ah, 0x9808, 1 << 27); in ar9271_hw_pa_cal()
460 REG_SET_BIT(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC); in ar9271_hw_pa_cal()
464 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I); in ar9271_hw_pa_cal()
529 REG_SET_BIT(ah, AR9285_AN_RF2G6, 1 << 0); in ar9271_hw_pa_cal()
751 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
754 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
782 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
860 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9002_hw_init_cal()
[all …]
H A Dmac.c149 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_abort_tx_dma()
413 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR | in ath9k_hw_resettxqueue()
437 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN); in ath9k_hw_resettxqueue()
443 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
448 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
471 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
480 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
488 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1); in ath9k_hw_resettxqueue()
498 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
644 REG_SET_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort()
[all …]
H A Dcalib.c234 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_start_nfcal()
241 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_start_nfcal()
244 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NF); in ath9k_hw_start_nfcal()
302 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NF); in ath9k_hw_loadnf()
324 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_loadnf()
327 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_loadnf()
329 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NF); in ath9k_hw_loadnf()
H A Dar9003_phy.c670 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar9003_hw_set_chain_masks()
1145 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1629 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1631 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1633 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1635 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1637 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1758 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1776 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_trigger()
1779 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_trigger()
[all …]
H A Dhw.c742 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
1411 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); in ath9k_hw_set_reset()
1697 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
2011 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset()
2197 REG_SET_BIT(ah, AR_RTC_RESET(ah), in ath9k_hw_set_power_awake()
2200 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah), in ath9k_hw_set_power_awake()
2212 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah), in ath9k_hw_set_power_awake()
2292 REG_SET_BIT(ah, AR_TXCFG, in ath9k_hw_beaconinit()
2317 REG_SET_BIT(ah, AR_TIMER_MODE, flags); in ath9k_hw_beaconinit()
2380 REG_SET_BIT(ah, AR_TIMER_MODE, in ath9k_hw_set_sta_beacon_timers()
[all …]
H A Dar9002_hw.c320 REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave()
374 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
376 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); in ar9002_hw_enable_async_fifo()
379 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
H A Dar9003_mci.c461 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), AR_GPIO_JTAG_DISABLE); in ar9003_mci_observation_set_up()
465 REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL, ATH_MCI_CONFIG_MCI_OBS_GPIO); in ar9003_mci_observation_set_up()
777 REG_SET_BIT(ah, AR_PHY_TIMING4, in ar9003_mci_end_reset()
795 REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); in ar9003_mci_mute_bt()
958 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, in ar9003_mci_reset()
983 REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN); in ar9003_mci_reset()
1020 REG_SET_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_reset()
1155 REG_SET_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_2g5g_switch()
1157 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, in ar9003_mci_2g5g_switch()
1413 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); in ar9003_mci_bt_gain_ctrl()
[all …]
H A Dar9003_aic.c255 REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_CH_VALID_RESET); in ar9003_aic_cal_start()
256 REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE); in ar9003_aic_cal_start()
510 REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, in ar9003_aic_cal_continue()
512 REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE); in ar9003_aic_cal_continue()
H A Dar9003_calib.c59 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); in ar9003_hw_setup_calibration()
300 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, in ar9003_hw_iqcalibrate()
370 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection()
388 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_dynamic_osdac_selection()
536 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_dynamic_osdac_selection()
542 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah), in ar9003_hw_dynamic_osdac_selection()
1444 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_init_cal_pcoem()
1465 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah), in ar9003_hw_init_cal_pcoem()
1591 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9003_hw_init_cal_soc()
H A Dar5008_phy.c600 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
627 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
645 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar5008_hw_override_ini()
781 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); in ar5008_hw_process_ini()
1023 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1259 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
H A Dbtcoex.c180 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), in ath9k_hw_btcoex_init_2wire()
200 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), in ath9k_hw_btcoex_init_3wire()
H A Dar9003_paprd.c942 REG_SET_BIT(ah, AR_PHY_CHAN_INFO_MEMORY(ah), in ar9003_paprd_create_curve()
H A Dar9003_hw.c1035 REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA); in ar9003_hw_configpcipowersave()
H A Dhw.h127 #define REG_SET_BIT(_a, _r, _f) \ macro
H A Dar9003_eeprom.c3697 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE); in ar9003_hw_ant_ctrl_apply()
3744 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_ant_ctrl_apply()
3748 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_ant_ctrl_apply()