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Searched refs:REG_READ_DATA_SAMPLE_DELAYS_ADDR (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c154 reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR) & in ddr3_read_leveling_hw()
219 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_read_leveling_sw()
224 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg); in ddr3_read_leveling_sw()
616 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_read_leveling_single_cs_rl_mode()
623 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, in ddr3_read_leveling_single_cs_rl_mode()
1021 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_read_leveling_single_cs_window_mode()
1028 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, in ddr3_read_leveling_single_cs_window_mode()
H A Dddr3_dfs.c707 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_dfs_high_2_low()
711 dfs_reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg); in ddr3_dfs_high_2_low()
1507 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_dfs_low_2_high()
1512 dfs_reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg); in ddr3_dfs_low_2_high()
H A Dddr3_hw_training.c764 *sdram_offset = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_save_training()
855 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, val); /* reg 0x1538 */ in ddr3_read_training_results()
1091 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_odt_read_dynamic_config()
H A Dddr3_axp.h198 #define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538 macro
H A Dddr3_init.c112 debug_print_reg(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in print_dunit_setup()
H A Dddr3_spd.c1041 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg);