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Searched refs:REG_PHY_REGISTRY_FILE_ACCESS_OP_WR (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c563 reg |= REG_PHY_REGISTRY_FILE_ACCESS_OP_WR; in ddr3_write_pup_reg()
584 reg |= REG_PHY_REGISTRY_FILE_ACCESS_OP_WR; in ddr3_write_pup_reg()
837 val |= REG_PHY_REGISTRY_FILE_ACCESS_OP_WR; in ddr3_read_training_results()
845 val |= REG_PHY_REGISTRY_FILE_ACCESS_OP_WR; in ddr3_read_training_results()
H A Dddr3_axp.h304 #define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xC0000000 macro
H A Dddr3_write_leveling.c1358 reg |= REG_PHY_REGISTRY_FILE_ACCESS_OP_WR; in ddr3_write_ctrl_pup_reg()
H A Dddr3_pbs.c1514 reg |= REG_PHY_REGISTRY_FILE_ACCESS_OP_WR; in ddr3_pbs_write_pup_dqs_reg()