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Searched refs:REG_MBOX0_WR (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/hw/intc/
H A Dbcm2836_control.c35 #define REG_MBOX0_WR 0x80 macro
264 } else if (offset >= REG_FIQSRC && offset < REG_MBOX0_WR) { in bcm2836_control_read()
293 } else if (offset >= REG_MBOX0_WR && offset < REG_MBOX0_RDCLR) { in bcm2836_control_write()
294 s->mailboxes[(offset - REG_MBOX0_WR) >> 2] |= val; in bcm2836_control_write()