Searched refs:REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 (Results 1 – 2 of 2) sorted by relevance
106 #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0 macro
1042 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3, timing->clk_trail); in dsi_7nm_phy_enable()