Searched refs:REG_DSI_7nm_PHY_CMN_CLK_CFG0 (Results 1 – 2 of 2) sorted by relevance
64 #define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010 macro
544 cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); in dsi_7nm_pll_save_state()569 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, in dsi_7nm_pll_restore_state()667 pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, in pll_7nm_register()742 pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, in pll_7nm_register()