Searched refs:REG_DSI_28nm_8960_PHY_PLL_CTRL_1 (Results 1 – 2 of 2) sorted by relevance
242 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004 macro
106 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, in dsi_pll_28nm_clk_set_rate()155 fb_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); in dsi_pll_28nm_clk_recalc_rate()