Searched refs:REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 (Results 1 – 2 of 2) sorted by relevance
188 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4 macro
245 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1, in dsi_pll_commit()436 frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) & in dsi_pll_10nm_vco_recalc_rate()