Searched refs:REG_DSI_10nm_PHY_CMN_CLK_CFG1 (Results 1 – 2 of 2) sorted by relevance
330 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); in dsi_pll_disable_global_clk()331 dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, in dsi_pll_disable_global_clk()339 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); in dsi_pll_enable_global_clk()340 dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, in dsi_pll_enable_global_clk()499 cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); in dsi_10nm_pll_save_state()523 val = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); in dsi_10nm_pll_restore_state()526 dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); in dsi_10nm_pll_restore_state()564 dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2)); in dsi_10nm_set_usecase()664 REG_DSI_10nm_PHY_CMN_CLK_CFG1, 0, 2, 0, NULL); in pll_10nm_register()
66 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014 macro