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Searched refs:REG_DRAM_TRAINING_2_WL_MODE_OFFS (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c713 ~(1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS); in ddr3_write_leveling_sw()
824 reg |= (1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS); in ddr3_write_leveling_sw()
948 ~(1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS); in ddr3_write_leveling_sw_reg_dimm()
1056 reg |= (1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS); in ddr3_write_leveling_sw_reg_dimm()
H A Dddr3_axp.h235 #define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2 macro