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Searched refs:REG_DRAM_TRAINING_2_SW_OVRD_OFFS (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c219 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_wl_supplement()
451 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_wl_supplement()
705 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_write_leveling_sw()
831 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_write_leveling_sw()
940 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_write_leveling_sw_reg_dimm()
1063 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_write_leveling_sw_reg_dimm()
H A Dddr3_pbs.c109 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_pbs_tx()
382 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_pbs_tx()
552 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_pbs_rx()
681 + (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS)); in ddr3_pbs_rx()
894 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_pbs_rx()
H A Dddr3_dqs.c139 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_dqs_centralization_rx()
194 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_dqs_centralization_rx()
221 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_dqs_centralization_tx()
274 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_dqs_centralization_tx()
H A Dddr3_hw_training.c625 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_load_patterns()
644 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_load_patterns()
931 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS)); in ddr3_training_suspend_resume()
H A Dddr3_axp.h237 #define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0 macro
H A Dddr3_read_leveling.c189 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_read_leveling_sw()
319 ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS); in ddr3_read_leveling_sw()
H A Dddr3_sdram.c650 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS)); in ddr3_reset_phy_read_fifo()