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Searched refs:REG_CPU_DIV_CLK_CTRL_4_ADDR (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c299 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_4_ADDR, reg); in ddr3_dfs_high_2_low()
593 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_4_ADDR, reg); in ddr3_dfs_high_2_low()
898 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_4_ADDR, reg); in ddr3_dfs_low_2_high()
1312 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_4_ADDR, reg); in ddr3_dfs_low_2_high()
H A Dddr3_axp.h359 #define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710 macro