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Searched refs:REG_CPU_DIV_CLK_CTRL_1_ADDR (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c281 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_high_2_low()
508 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_high_2_low()
576 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_high_2_low()
883 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_low_2_high()
1209 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_low_2_high()
1295 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_low_2_high()
H A Dddr3_axp.h352 #define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704 macro