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Searched refs:REG_CON0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-pll.c20 #define REG_CON0 0 macro
231 r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask; in mtk_pll_prepare()
232 writel(r, pll->base_addr + REG_CON0); in mtk_pll_prepare()
240 r = readl(pll->base_addr + REG_CON0); in mtk_pll_prepare()
242 writel(r, pll->base_addr + REG_CON0); in mtk_pll_prepare()
254 r = readl(pll->base_addr + REG_CON0); in mtk_pll_unprepare()
256 writel(r, pll->base_addr + REG_CON0); in mtk_pll_unprepare()
262 r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask; in mtk_pll_unprepare()
263 writel(r, pll->base_addr + REG_CON0); in mtk_pll_unprepare()
309 pll->en_addr = pll->base_addr + REG_CON0; in mtk_clk_register_pll_ops()
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.c17 #define REG_CON0 0 macro
216 r = readl(priv->base + pll->reg + REG_CON0); in mtk_apmixedsys_enable()
218 writel(r, priv->base + pll->reg + REG_CON0); in mtk_apmixedsys_enable()
223 r = readl(priv->base + pll->reg + REG_CON0); in mtk_apmixedsys_enable()
225 writel(r, priv->base + pll->reg + REG_CON0); in mtk_apmixedsys_enable()
238 r = readl(priv->base + pll->reg + REG_CON0); in mtk_apmixedsys_disable()
240 writel(r, priv->base + pll->reg + REG_CON0); in mtk_apmixedsys_disable()
243 r = readl(priv->base + pll->reg + REG_CON0); in mtk_apmixedsys_disable()
245 writel(r, priv->base + pll->reg + REG_CON0); in mtk_apmixedsys_disable()