Searched refs:REG_CLK_CLKDIV0 (Results 1 – 1 of 1) sorted by relevance
33 #define REG_CLK_CLKDIV0 0x2c macro524 hws[AXICLK_MUX] = ma35d1_clk_mux(dev, "axiclk_mux", clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()559 clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()566 clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()573 clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()580 clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()617 clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()