Home
last modified time | relevance | path

Searched refs:REGV_WR64 (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/accel/ivpu/
H A Divpu_hw_40xx.c642 REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64); in ivpu_boot_soc_cpu_boot()
981 REGV_WR64(VPU_40XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK); in ivpu_hw_40xx_irq_clear()
987 REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK); in ivpu_hw_40xx_irq_enable()
996 REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, 0x0ull); in ivpu_hw_40xx_irq_disable()
H A Divpu_mmu.c509 REGV_WR64(VPU_37XX_HOST_MMU_STRTAB_BASE, mmu->strtab.dma_q); in ivpu_mmu_reset()
512 REGV_WR64(VPU_37XX_HOST_MMU_CMDQ_BASE, mmu->cmdq.dma_q); in ivpu_mmu_reset()
533 REGV_WR64(VPU_37XX_HOST_MMU_EVTQ_BASE, mmu->evtq.dma_q); in ivpu_mmu_reset()
H A Divpu_hw_reg_io.h28 #define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__) macro
H A Divpu_hw_37xx.c871 REGV_WR64(VPU_37XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK); in ivpu_hw_37xx_irq_clear()
877 REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK); in ivpu_hw_37xx_irq_enable()
886 REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull); in ivpu_hw_37xx_irq_disable()