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Searched refs:REGB_WR32 (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/accel/ivpu/
H A Divpu_hw_40xx.c174 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val); in ivpu_pll_cmd_send()
179 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, val); in ivpu_pll_cmd_send()
184 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2, val); in ivpu_pll_cmd_send()
188 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_CMD, val); in ivpu_pll_cmd_send()
425 REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS, WEIGHTS_DEFAULT); in ivpu_boot_host_ss_axi_drive()
426 REGB_WR32(VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS, WEIGHTS_ATS_DEFAULT); in ivpu_boot_host_ss_axi_drive()
670 REGB_WR32(VPU_40XX_BUTTRESS_D0I3_CONTROL, val); in ivpu_boot_d0i3_drive()
750 REGB_WR32(VPU_40XX_BUTTRESS_IP_RESET, val); in ivpu_hw_40xx_reset()
798 REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val); in ivpu_hw_40xx_profiling_freq_reg_set()
812 REGB_WR32(VPU_40XX_BUTTRESS_VPU_STATUS, val); in ivpu_hw_40xx_clock_relinquish_disable()
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H A Divpu_hw_37xx.c107 REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, BUTTRESS_ALL_IRQ_MASK); in ivpu_hw_wa_init()
111 REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0); in ivpu_hw_wa_init()
156 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, val); in ivpu_pll_cmd_send()
161 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, val); in ivpu_pll_cmd_send()
165 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, val); in ivpu_pll_cmd_send()
169 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_CMD, val); in ivpu_pll_cmd_send()
625 REGB_WR32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, val); in ivpu_boot_d0i3_drive()
878 REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK); in ivpu_hw_37xx_irq_enable()
879 REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0); in ivpu_hw_37xx_irq_enable()
884 REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1); in ivpu_hw_37xx_irq_disable()
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H A Divpu_hw_reg_io.h21 #define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__) macro