Searched refs:RCC_BDCR (Results 1 – 5 of 5) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-stm32mp/ |
| H A D | cpu.c | 19 #define RCC_BDCR (STM32_RCC_BASE + 0x0140) macro
75 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { in security_init()
76 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); in security_init()
77 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) in security_init()
79 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); in security_init()
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_stm32mp1.c | 65 #define RCC_BDCR 0x140 macro
1215 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP); in stm32mp1_lse_enable()
1218 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); in stm32mp1_lse_enable()
1224 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) in stm32mp1_lse_enable()
1233 clrsetbits_le32(rcc + RCC_BDCR, in stm32mp1_lse_enable()
1238 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON); in stm32mp1_lse_enable()
1243 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY); in stm32mp1_lse_wait()
1542 u32 address = priv->base + RCC_BDCR; in set_rtcsrc()
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-stm32h7.c | 38 #define RCC_BDCR 0x70 macro
1169 KER_CLK(RCC_BDCR, 15, RCC_BDCR, 8, 2, "rtc_ck", rtc_src);
1296 RCC_BDCR + base, in stm32h7_rcc_init()
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| H A D | clk-stm32mp1.c | 95 #define RCC_BDCR 0x140 macro
1768 GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
2060 _GATE(RCC_BDCR, 20, 0),
2061 _MUX(RCC_BDCR, 16, 2, 0),
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| /openbmc/linux/drivers/clk/stm32/ |
| H A D | stm32mp13_rcc.h | 25 #define RCC_BDCR 0x400 macro
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