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Searched refs:RB_BLKSZ (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c889 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_0_start_dpg_mode()
1061 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_0_start()
1976 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_0_start_sriov()
H A Dvcn_v2_5.c921 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_5_start_dpg_mode()
1113 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_5_start()
1332 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_5_sriov_start()
H A Duvd_v5_0.c418 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v5_0_start()
H A Dvcn_v3_0.c1046 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v3_0_start_dpg_mode()
1233 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v3_0_start()
1418 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v3_0_start_sriov()
H A Dvcn_v1_0.c913 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v1_0_start_spg_mode()
1071 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v1_0_start_dpg_mode()
H A Duvd_v6_0.c834 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v6_0_start()
H A Dsid.h1276 #define RB_BLKSZ(x) ((x) << 8) macro
H A Duvd_v7_0.c1083 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v7_0_start()
H A Dgfx_v11_0.c3259 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
3299 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
3654 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_gfx_mqd_init()
H A Dgfx_v10_0.c6103 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6146 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6405 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_gfx_mqd_init()
H A Dgfx_v8_0.c4254 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
H A Dgfx_v9_0.c3114 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drv770d.h351 #define RB_BLKSZ(x) ((x) << 8) macro
H A Dnid.h486 #define RB_BLKSZ(x) ((x) << 8) macro
H A Dsid.h1248 #define RB_BLKSZ(x) ((x) << 8) macro
H A Dcikd.h1304 #define RB_BLKSZ(x) ((x) << 8) macro
H A Drv770.c1102 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in rv770_cp_load_microcode()
H A Devergreend.h478 #define RB_BLKSZ(x) ((x) << 8) macro
H A Dr600d.h197 #define RB_BLKSZ(x) ((x) << 8) macro
H A Dr600.c2658 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in r600_cp_load_microcode()
H A Devergreen.c2980 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in evergreen_cp_load_microcode()