Searched refs:RALINK_PCIEPHY_P0_CTL_OFFSET (Results 1 – 1 of 1) sorted by relevance
65 #define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498 macro270 pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET); in mt7628_pci_hw_init()