Searched refs:R9A07G044_CLK_P0_DIV2 (Results 1 – 3 of 3) sorted by relevance
33 #define R9A07G044_CLK_P0_DIV2 22 macro
156 DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
515 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,518 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;