Searched refs:R9A07G044_CLK_I (Results 1 – 3 of 3) sorted by relevance
11 #define R9A07G044_CLK_I 0 macro
154 DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;