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Searched refs:R8A7790_CLK_ZS (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/drivers/clk/renesas/
H A Dr8a7790-cpg-mssr.c69 DEF_FIXED("zs", R8A7790_CLK_ZS, CLK_PLL1, 6, 1),
95 DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
96 DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
97 DEF_MOD("vpc1", 102, R8A7790_CLK_ZS),
98 DEF_MOD("vpc0", 103, R8A7790_CLK_ZS),
100 DEF_MOD("ssp1", 109, R8A7790_CLK_ZS),
103 DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
104 DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
105 DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
106 DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS),
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Dr8a7790-cpg-mssr.c67 DEF_FIXED("zs", R8A7790_CLK_ZS, CLK_PLL1, 6, 1),
93 DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
94 DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
95 DEF_MOD("vpc1", 102, R8A7790_CLK_ZS),
96 DEF_MOD("vpc0", 103, R8A7790_CLK_ZS),
98 DEF_MOD("ssp1", 109, R8A7790_CLK_ZS),
101 DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
102 DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
103 DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
104 DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS),
[all …]
/openbmc/linux/include/dt-bindings/clock/
H A Dr8a7790-cpg-mssr.h19 #define R8A7790_CLK_ZS 7 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dr8a7790-cpg-mssr.h23 #define R8A7790_CLK_ZS 7 macro
/openbmc/u-boot/arch/arm/dts/
H A Dr8a7790.dtsi888 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
905 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
922 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
938 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
954 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7790.dtsi911 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
928 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
945 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
961 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
977 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;