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/openbmc/linux/arch/hexagon/kernel/
H A Dvm_entry.S70 R2 = and(R0,R2); } \
215 R0 = R29; \
232 R0 = usr; \
236 R0 = setbit(R0, #16); \
238 usr = R0; \
246 R0 = R29; \
274 R0 = #VM_INT_DISABLE define
287 R0 = #VM_INT_DISABLE; define
308 R0 = #VM_INT_DISABLE; define
331 R0 = R29 define
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H A Dvm_switch.S55 memw(R0+#_TASK_THREAD_INFO) = THREADINFO_REG;
56 memw(R0 +#(_TASK_STRUCT_THREAD + _THREAD_STRUCT_SWITCH_SP)) = R29;
/openbmc/linux/lib/
H A Dtest_bpf.c1947 else if (R0 == rd || R0 == rs) in __bpf_fill_atomic_reg_pairs()
3808 BPF_ALU64_REG(BPF_ADD, R0, R0),
4092 BPF_ALU64_REG(BPF_SUB, R0, R0),
4215 BPF_ALU64_REG(BPF_SUB, R0, R0),
4263 BPF_ALU64_REG(BPF_XOR, R0, R0),
4267 BPF_ALU64_REG(BPF_XOR, R0, R0),
4291 BPF_ALU64_REG(BPF_MUL, R0, R0),
4363 BPF_ALU64_REG(BPF_ADD, R0, R0),
4403 BPF_ALU64_REG(BPF_ADD, R0, R0),
4443 BPF_ALU64_REG(BPF_ADD, R0, R0),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8365-pinctrl.yaml83 100: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
84 101: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
85 102: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
86 103: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
98 101: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
99 102: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
100 103: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
156 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
157 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
158 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
[all …]
H A Dmediatek,mt6795-pinctrl.yaml101 description: mt6795 pull down PUPD/R0/R1 type define value.
111 description: mt6795 pull up PUPD/R0/R1 type define value.
133 Pull up settings for 2 pull resistors, R0 and R1. User can
136 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
137 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
138 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
139 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
148 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
149 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
150 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
[all …]
H A Dmediatek,mt6779-pinctrl.yaml162 Pull up settings for 2 pull resistors, R0 and R1. User can
165 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
166 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
167 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
168 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
174 Pull down settings for 2 pull resistors, R0 and R1. User can
177 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
178 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
179 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
180 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
H A Dmediatek,mt8183-pinctrl.yaml146 Pull up settings for 2 pull resistors, R0 and R1. User can
149 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
150 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
151 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
152 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
158 Pull down settings for 2 pull resistors, R0 and R1. User can
161 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
162 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
163 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
164 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
H A Dmediatek,mt7986-pinctrl.yaml303 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
312 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
335 Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
337 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
338 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
339 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
340 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
349 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
350 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
351 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
[all …]
H A Dmediatek,mt7981-pinctrl.yaml357 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
366 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
389 Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
391 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
392 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
393 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
394 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
403 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
404 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
405 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
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/openbmc/linux/arch/x86/crypto/
H A Dtwofish-x86_64-asm_64.S29 #define R0 %rax macro
226 encrypt_round(R0,R1,R2,R3,0);
227 encrypt_round(R2,R3,R0,R1,8);
228 encrypt_round(R0,R1,R2,R3,2*8);
229 encrypt_round(R2,R3,R0,R1,3*8);
230 encrypt_round(R0,R1,R2,R3,4*8);
231 encrypt_round(R2,R3,R0,R1,5*8);
232 encrypt_round(R0,R1,R2,R3,6*8);
233 encrypt_round(R2,R3,R0,R1,7*8);
248 xor R0, R1
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H A Dtwofish-i586-asm_32.S231 encrypt_round(R0,R1,R2,R3,0);
232 encrypt_round(R2,R3,R0,R1,8);
233 encrypt_round(R0,R1,R2,R3,2*8);
234 encrypt_round(R2,R3,R0,R1,3*8);
235 encrypt_round(R0,R1,R2,R3,4*8);
236 encrypt_round(R2,R3,R0,R1,5*8);
237 encrypt_round(R0,R1,R2,R3,6*8);
238 encrypt_round(R2,R3,R0,R1,7*8);
239 encrypt_round(R0,R1,R2,R3,8*8);
240 encrypt_round(R2,R3,R0,R1,9*8);
[all …]
H A Dpoly1305-x86_64-cryptogams.pl2298 vpmuludq $T1,$R0,$M1
2313 vpmuludq $T2,$R0,$M2
2399 vpermd $R0,$M0,$R0 # 14243444 -> 1---2---3---4---
2595 vpsrlq \$32,$R0,$R0 # 0105020603070408
3099 vmovdqa $R0,$H0
3171 vpunpcklqdq $R0,$H0,$R0
3188 vinserti128 \$1,%x#$R0,$H0,$R0
3192 vpermq \$0b11011000,$R0,$R0
3206 vpbroadcastq %x#$R0,$R0 # broadcast 4th power
3220 vpsrldq \$8,$R0,$R0 # 0-1-0-2
[all …]
/openbmc/linux/arch/arm/crypto/
H A Dpoly1305-armv4.pl554 vmull.u32 $D0,$R0,${R0}[1]
1064 vmull.u32 $D2,$H2#hi,$R0
1066 vmull.u32 $D0,$H0#hi,$R0
1068 vmull.u32 $D3,$H3#hi,$R0
1070 vmull.u32 $D1,$H1#hi,$R0
1072 vmull.u32 $D4,$H4#hi,$R0
1116 vmlal.u32 $D2,$H2#lo,$R0
1117 vmlal.u32 $D0,$H0#lo,$R0
1118 vmlal.u32 $D3,$H3#lo,$R0
1119 vmlal.u32 $D1,$H1#lo,$R0
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dpoly1305-armv8.pl577 umull $ACC0,$IN23_0,${R0}[2]
760 umull2 $ACC2,$IN23_2,${R0}
764 umlal2 $ACC0,$IN23_0,${R0}
775 umlal2 $ACC1,$IN23_1,${R0}
778 umlal2 $ACC3,$IN23_3,${R0}
786 umlal2 $ACC4,$IN23_4,${R0}
800 umlal $ACC2,$IN01_2,${R0}
804 umlal $ACC0,$IN01_0,${R0}
813 umlal $ACC1,$IN01_1,${R0}
817 umlal $ACC3,$IN01_3,${R0}
[all …]
/openbmc/qemu/tests/tcg/multiarch/
H A Dsha1.c63 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30); macro
97 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); in SHA1Transform()
98 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); in SHA1Transform()
99 R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); in SHA1Transform()
100 R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); in SHA1Transform()
/openbmc/linux/arch/sh/kernel/cpu/sh3/
H A Dswsusp.S59 ! BL=0: R7->R0 is bank0
65 ! BL=1: R7->R0 is bank1
80 ! BL=0: R7->R0 is bank0
105 ! BL=0: R7->R0 is bank0
112 ! BL=1: R7->R0 is bank1
119 ! BL=0: R7->R0 is bank0
/openbmc/linux/drivers/tty/serial/
H A Dpmac_zilog.c162 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
163 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
229 write_zsreg(uap, R0, ERR_RES); in pmz_receive_chars()
293 ch = read_zsreg(uap, R0); in pmz_receive_chars()
305 status = read_zsreg(uap, R0); in pmz_status_handle()
407 write_zsreg(uap, R0, RES_Tx_P); in pmz_transmit_chars()
487 status = read_zsreg(uap, R0); in pmz_peek_status()
559 status = read_zsreg(uap, R0); in pmz_get_mctrl()
594 status = read_zsreg(uap, R0); in pmz_start_tx()
817 write_zsreg(uap, R0, ERR_RES); in __pmz_startup()
[all …]
H A Dzs.c324 status_a = read_zsreg(zport_a, R0); in zs_raw_get_ab_mctrl()
325 status_b = read_zsreg(zport_b, R0); in zs_raw_get_ab_mctrl()
421 write_zsreg(zport, R0, RES_Tx_P); in zs_raw_stop_tx()
498 write_zsreg(zport_a, R0, RES_EXT_INT); in zs_enable_ms()
573 write_zsreg(zport, R0, ERR_RES); in zs_receive_chars()
656 status = read_zsreg(zport, R0); in zs_status_handle()
693 write_zsreg(zport, R0, RES_EXT_INT); in zs_status_handle()
778 write_zsreg(zport, R0, ERR_RES); in zs_startup()
779 write_zsreg(zport, R0, RES_Tx_P); in zs_startup()
782 write_zsreg(zport, R0, RES_EXT_INT); in zs_startup()
[all …]
/openbmc/openbmc/poky/meta/recipes-multimedia/mpeg2dec/files/
H A D0001-Import-revision-1206-from-upstream-to-fix-PIE-build.patch110 .macro ADJ_ALIGN_QW shift, R0, R1, R2, R3, R4
111 mov \R0, \R0, lsr #(\shift)
145 .macro ADJ_ALIGN_DW shift, R0, R1, R2
146 mov \R0, \R0, lsr #(\shift)
/openbmc/linux/arch/sh/math-emu/
H A Dmath.c50 #define R0 (regs->regs[0]) macro
160 MREAD(FRn, Rm + R0 + 4); in fmov_idx_reg()
162 MREAD(FRn, Rm + R0); in fmov_idx_reg()
164 MREAD(FRn, Rm + R0); in fmov_idx_reg()
210 MWRITE(FRm, Rn + R0 + 4); in fmov_reg_idx()
212 MWRITE(FRm, Rn + R0); in fmov_reg_idx()
214 MWRITE(FRm, Rn + R0); in fmov_reg_idx()
/openbmc/linux/tools/perf/arch/arm/tests/
H A Dregs_load.S4 #define R0 0x00 macro
41 str r0, [r0, #R0]
/openbmc/linux/Documentation/bpf/standardization/
H A Dabi.rst19 * R0: return value from function calls, and exit value for BPF programs
24 R0 - R5 are scratch registers and BPF programs needs to spill/fill them if
/openbmc/linux/tools/perf/arch/powerpc/tests/
H A Dregs_load.S5 #define R0 0 macro
44 std 0, R0(3)
/openbmc/linux/arch/powerpc/mm/nohash/
H A Dtlb_low.S244 PPC_TLBILX_ALL(0,R0)
257 PPC_TLBILX_PID(0,R0)
309 PPC_TLBILX_PID(0,R0)
321 PPC_TLBILX_PID(0,R0)
328 PPC_TLBILX_ALL(0,R0)
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dlowlevel_init.S41 MRC p15, 4, R0, c1, c0, 0
44 MCR p15, 4, R0, c1, c0, 0

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