| /openbmc/qemu/tests/tcg/multiarch/ |
| H A D | sha1.c | 63 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30); macro
97 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); in SHA1Transform()
98 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); in SHA1Transform()
99 R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); in SHA1Transform()
100 R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); in SHA1Transform()
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| /openbmc/u-boot/arch/arm/mach-omap2/ |
| H A D | lowlevel_init.S | 41 MRC p15, 4, R0, c1, c0, 0
44 MCR p15, 4, R0, c1, c0, 0
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| /openbmc/qemu/target/avr/ |
| H A D | translate.c | 716 TCGv R0 = cpu_r[0]; in trans_MUL() local
723 tcg_gen_andi_tl(R0, R, 0xff); in trans_MUL()
741 TCGv R0 = cpu_r[0]; in trans_MULS() local
753 tcg_gen_andi_tl(R0, R, 0xff); in trans_MULS()
772 TCGv R0 = cpu_r[0]; in trans_MULSU() local
782 tcg_gen_andi_tl(R0, R, 0xff); in trans_MULSU()
801 TCGv R0 = cpu_r[0]; in trans_FMUL() local
815 tcg_gen_andi_tl(R0, R, 0xff); in trans_FMUL()
831 TCGv R0 = cpu_r[0]; in trans_FMULS() local
850 tcg_gen_andi_tl(R0, R, 0xff); in trans_FMULS()
[all …]
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/ |
| H A D | spr_lowlevel_init.S | 115 ldr r1,[R0]
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| /openbmc/qemu/target/openrisc/ |
| H A D | translate.c | 57 TCGv R0; member
165 return dc->R0; in cpu_R()
178 dc->R0 = cpu_regs[0]; in check_r0_write()
1549 dc->R0 = dc->zero; in openrisc_tr_tb_start()
1551 dc->R0 = cpu_regs[0]; in openrisc_tr_tb_start()
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| /openbmc/qemu/tests/tcg/hexagon/ |
| H A D | hvx_histogram_row.S | 79 { v12.tmp = vmem(R0++#1)
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| /openbmc/libcper/include/libcper/ |
| H A D | Cper.h | 1530 UINT32 R0; member
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| /openbmc/qemu/target/hexagon/idef-parser/ |
| H A D | README.rst | 607 61 | 0x0002109c: 0x707dc000 { R0 = R29 }
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| /openbmc/qemu/tcg/s390x/ |
| H A D | tcg-target.c.inc | 2433 * result into R0, allowing R1 == TCG_TMP0 to be clobbered as well.
3779 /* XXX many insns can't be used with R0, so we better avoid it for now */
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| /openbmc/qemu/tcg/ppc/ |
| H A D | tcg-target.c.inc | 69 /* For some memory operations, we need a scratch that isn't R0. For the AIX
2472 /* Clear the non-page, non-alignment bits from the address in R0. */
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| /openbmc/qemu/tcg/arm/ |
| H A D | tcg-target.c.inc | 1429 /* Extract the tlb index from the address into R0. */
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| /openbmc/u-boot/ |
| H A D | README | 4675 R0: function argument word/integer result
4699 R0-R1: argument/return
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| /openbmc/libcper/specification/document/ |
| H A D | cper-json-specification.tex | 948 r0 & uint64 & Register R0. \texttt{UINT32} value null extended to \texttt{UINT64}.\\
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