1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * NVIDIA Tegra210 QSPI controller driver
4 *
5 * (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com>
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch-tegra/clk_rst.h>
13 #include <spi.h>
14 #include <fdtdec.h>
15 #include "tegra_spi.h"
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 /* COMMAND1 */
20 #define QSPI_CMD1_GO BIT(31)
21 #define QSPI_CMD1_M_S BIT(30)
22 #define QSPI_CMD1_MODE_MASK GENMASK(1,0)
23 #define QSPI_CMD1_MODE_SHIFT 28
24 #define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0)
25 #define QSPI_CMD1_CS_SEL_SHIFT 26
26 #define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22)
27 #define QSPI_CMD1_CS_SW_HW BIT(21)
28 #define QSPI_CMD1_CS_SW_VAL BIT(20)
29 #define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0)
30 #define QSPI_CMD1_IDLE_SDA_SHIFT 18
31 #define QSPI_CMD1_BIDIR BIT(17)
32 #define QSPI_CMD1_LSBI_FE BIT(16)
33 #define QSPI_CMD1_LSBY_FE BIT(15)
34 #define QSPI_CMD1_BOTH_EN_BIT BIT(14)
35 #define QSPI_CMD1_BOTH_EN_BYTE BIT(13)
36 #define QSPI_CMD1_RX_EN BIT(12)
37 #define QSPI_CMD1_TX_EN BIT(11)
38 #define QSPI_CMD1_PACKED BIT(5)
39 #define QSPI_CMD1_BITLEN_MASK GENMASK(4,0)
40 #define QSPI_CMD1_BITLEN_SHIFT 0
41
42 /* COMMAND2 */
43 #define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
44 #define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6)
45 #define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
46 #define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0)
47
48 /* TRANSFER STATUS */
49 #define QSPI_XFER_STS_RDY BIT(30)
50
51 /* FIFO STATUS */
52 #define QSPI_FIFO_STS_CS_INACTIVE BIT(31)
53 #define QSPI_FIFO_STS_FRAME_END BIT(30)
54 #define QSPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
55 #define QSPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
56 #define QSPI_FIFO_STS_ERR BIT(8)
57 #define QSPI_FIFO_STS_TX_FIFO_OVF BIT(7)
58 #define QSPI_FIFO_STS_TX_FIFO_UNR BIT(6)
59 #define QSPI_FIFO_STS_RX_FIFO_OVF BIT(5)
60 #define QSPI_FIFO_STS_RX_FIFO_UNR BIT(4)
61 #define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3)
62 #define QSPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
63 #define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1)
64 #define QSPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
65
66 #define QSPI_TIMEOUT 1000
67
68 struct qspi_regs {
69 u32 command1; /* 000:QSPI_COMMAND1 register */
70 u32 command2; /* 004:QSPI_COMMAND2 register */
71 u32 timing1; /* 008:QSPI_CS_TIM1 register */
72 u32 timing2; /* 00c:QSPI_CS_TIM2 register */
73 u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */
74 u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */
75 u32 tx_data; /* 018:QSPI_TX_DATA register */
76 u32 rx_data; /* 01c:QSPI_RX_DATA register */
77 u32 dma_ctl; /* 020:QSPI_DMA_CTL register */
78 u32 dma_blk; /* 024:QSPI_DMA_BLK register */
79 u32 rsvd[56]; /* 028-107 reserved */
80 u32 tx_fifo; /* 108:QSPI_FIFO1 register */
81 u32 rsvd2[31]; /* 10c-187 reserved */
82 u32 rx_fifo; /* 188:QSPI_FIFO2 register */
83 u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */
84 };
85
86 struct tegra210_qspi_priv {
87 struct qspi_regs *regs;
88 unsigned int freq;
89 unsigned int mode;
90 int periph_id;
91 int valid;
92 int last_transaction_us;
93 };
94
tegra210_qspi_ofdata_to_platdata(struct udevice * bus)95 static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
96 {
97 struct tegra_spi_platdata *plat = bus->platdata;
98 const void *blob = gd->fdt_blob;
99 int node = dev_of_offset(bus);
100
101 plat->base = devfdt_get_addr(bus);
102 plat->periph_id = clock_decode_periph_id(bus);
103
104 if (plat->periph_id == PERIPH_ID_NONE) {
105 debug("%s: could not decode periph id %d\n", __func__,
106 plat->periph_id);
107 return -FDT_ERR_NOTFOUND;
108 }
109
110 /* Use 500KHz as a suitable default */
111 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
112 500000);
113 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
114 "spi-deactivate-delay", 0);
115 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
116 __func__, plat->base, plat->periph_id, plat->frequency,
117 plat->deactivate_delay_us);
118
119 return 0;
120 }
121
tegra210_qspi_probe(struct udevice * bus)122 static int tegra210_qspi_probe(struct udevice *bus)
123 {
124 struct tegra_spi_platdata *plat = dev_get_platdata(bus);
125 struct tegra210_qspi_priv *priv = dev_get_priv(bus);
126
127 priv->regs = (struct qspi_regs *)plat->base;
128
129 priv->last_transaction_us = timer_get_us();
130 priv->freq = plat->frequency;
131 priv->periph_id = plat->periph_id;
132
133 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
134 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
135
136 return 0;
137 }
138
tegra210_qspi_claim_bus(struct udevice * bus)139 static int tegra210_qspi_claim_bus(struct udevice *bus)
140 {
141 struct tegra210_qspi_priv *priv = dev_get_priv(bus);
142 struct qspi_regs *regs = priv->regs;
143
144 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
145 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
146
147 debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status));
148
149 /* Set master mode and sw controlled CS */
150 setbits_le32(®s->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW |
151 (priv->mode << QSPI_CMD1_MODE_SHIFT));
152 debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1));
153
154 return 0;
155 }
156
157 /**
158 * Activate the CS by driving it LOW
159 *
160 * @param slave Pointer to spi_slave to which controller has to
161 * communicate with
162 */
spi_cs_activate(struct udevice * dev)163 static void spi_cs_activate(struct udevice *dev)
164 {
165 struct udevice *bus = dev->parent;
166 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
167 struct tegra210_qspi_priv *priv = dev_get_priv(bus);
168
169 /* If it's too soon to do another transaction, wait */
170 if (pdata->deactivate_delay_us &&
171 priv->last_transaction_us) {
172 ulong delay_us; /* The delay completed so far */
173 delay_us = timer_get_us() - priv->last_transaction_us;
174 if (delay_us < pdata->deactivate_delay_us)
175 udelay(pdata->deactivate_delay_us - delay_us);
176 }
177
178 clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
179 }
180
181 /**
182 * Deactivate the CS by driving it HIGH
183 *
184 * @param slave Pointer to spi_slave to which controller has to
185 * communicate with
186 */
spi_cs_deactivate(struct udevice * dev)187 static void spi_cs_deactivate(struct udevice *dev)
188 {
189 struct udevice *bus = dev->parent;
190 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
191 struct tegra210_qspi_priv *priv = dev_get_priv(bus);
192
193 setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
194
195 /* Remember time of this transaction so we can honour the bus delay */
196 if (pdata->deactivate_delay_us)
197 priv->last_transaction_us = timer_get_us();
198
199 debug("Deactivate CS, bus '%s'\n", bus->name);
200 }
201
tegra210_qspi_xfer(struct udevice * dev,unsigned int bitlen,const void * data_out,void * data_in,unsigned long flags)202 static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen,
203 const void *data_out, void *data_in,
204 unsigned long flags)
205 {
206 struct udevice *bus = dev->parent;
207 struct tegra210_qspi_priv *priv = dev_get_priv(bus);
208 struct qspi_regs *regs = priv->regs;
209 u32 reg, tmpdout, tmpdin = 0;
210 const u8 *dout = data_out;
211 u8 *din = data_in;
212 int num_bytes, tm, ret;
213
214 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
215 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
216 if (bitlen % 8)
217 return -1;
218 num_bytes = bitlen / 8;
219
220 ret = 0;
221
222 /* clear all error status bits */
223 reg = readl(®s->fifo_status);
224 writel(reg, ®s->fifo_status);
225
226 /* flush RX/TX FIFOs */
227 setbits_le32(®s->fifo_status,
228 (QSPI_FIFO_STS_RX_FIFO_FLUSH |
229 QSPI_FIFO_STS_TX_FIFO_FLUSH));
230
231 tm = QSPI_TIMEOUT;
232 while ((tm && readl(®s->fifo_status) &
233 (QSPI_FIFO_STS_RX_FIFO_FLUSH |
234 QSPI_FIFO_STS_TX_FIFO_FLUSH))) {
235 tm--;
236 udelay(1);
237 }
238
239 if (!tm) {
240 printf("%s: timeout during QSPI FIFO flush!\n",
241 __func__);
242 return -1;
243 }
244
245 /*
246 * Notes:
247 * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs;
248 * 2. don't set RX_EN and TX_EN yet.
249 * (SW needs to make sure that while programming the blk_size,
250 * tx_en and rx_en bits must be zero)
251 * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set
252 * i.e., both dout and din are not NULL.
253 */
254 clrsetbits_le32(®s->command1,
255 (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE |
256 QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN),
257 (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT));
258
259 /* set xfer size to 1 block (32 bits) */
260 writel(0, ®s->dma_blk);
261
262 if (flags & SPI_XFER_BEGIN)
263 spi_cs_activate(dev);
264
265 /* handle data in 32-bit chunks */
266 while (num_bytes > 0) {
267 int bytes;
268
269 tmpdout = 0;
270 bytes = (num_bytes > 4) ? 4 : num_bytes;
271
272 if (dout != NULL) {
273 memcpy((void *)&tmpdout, (void *)dout, bytes);
274 dout += bytes;
275 num_bytes -= bytes;
276 writel(tmpdout, ®s->tx_fifo);
277 setbits_le32(®s->command1, QSPI_CMD1_TX_EN);
278 }
279
280 if (din != NULL)
281 setbits_le32(®s->command1, QSPI_CMD1_RX_EN);
282
283 /* clear ready bit */
284 setbits_le32(®s->xfer_status, QSPI_XFER_STS_RDY);
285
286 clrsetbits_le32(®s->command1,
287 QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT,
288 (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT);
289
290 /* Need to stabilize other reg bits before GO bit set.
291 * As per the TRM:
292 * "For successful operation at various freq combinations,
293 * a minimum of 4-5 spi_clk cycle delay might be required
294 * before enabling the PIO or DMA bits. The worst case delay
295 * calculation can be done considering slowest qspi_clk as
296 * 1MHz. Based on that 1us delay should be enough before
297 * enabling PIO or DMA." Padded another 1us for safety.
298 */
299 udelay(2);
300 setbits_le32(®s->command1, QSPI_CMD1_GO);
301 udelay(1);
302
303 /*
304 * Wait for SPI transmit FIFO to empty, or to time out.
305 * The RX FIFO status will be read and cleared last
306 */
307 for (tm = 0; tm < QSPI_TIMEOUT; ++tm) {
308 u32 fifo_status, xfer_status;
309
310 xfer_status = readl(®s->xfer_status);
311 if (!(xfer_status & QSPI_XFER_STS_RDY))
312 continue;
313
314 fifo_status = readl(®s->fifo_status);
315 if (fifo_status & QSPI_FIFO_STS_ERR) {
316 debug("%s: got a fifo error: ", __func__);
317 if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF)
318 debug("tx FIFO overflow ");
319 if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR)
320 debug("tx FIFO underrun ");
321 if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF)
322 debug("rx FIFO overflow ");
323 if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR)
324 debug("rx FIFO underrun ");
325 if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL)
326 debug("tx FIFO full ");
327 if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY)
328 debug("tx FIFO empty ");
329 if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL)
330 debug("rx FIFO full ");
331 if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)
332 debug("rx FIFO empty ");
333 debug("\n");
334 break;
335 }
336
337 if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) {
338 tmpdin = readl(®s->rx_fifo);
339 if (din != NULL) {
340 memcpy(din, &tmpdin, bytes);
341 din += bytes;
342 num_bytes -= bytes;
343 }
344 }
345 break;
346 }
347
348 if (tm >= QSPI_TIMEOUT)
349 ret = tm;
350
351 /* clear ACK RDY, etc. bits */
352 writel(readl(®s->fifo_status), ®s->fifo_status);
353 }
354
355 if (flags & SPI_XFER_END)
356 spi_cs_deactivate(dev);
357
358 debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
359 __func__, tmpdin, readl(®s->fifo_status));
360
361 if (ret) {
362 printf("%s: timeout during SPI transfer, tm %d\n",
363 __func__, ret);
364 return -1;
365 }
366
367 return ret;
368 }
369
tegra210_qspi_set_speed(struct udevice * bus,uint speed)370 static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
371 {
372 struct tegra_spi_platdata *plat = bus->platdata;
373 struct tegra210_qspi_priv *priv = dev_get_priv(bus);
374
375 if (speed > plat->frequency)
376 speed = plat->frequency;
377 priv->freq = speed;
378 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
379
380 return 0;
381 }
382
tegra210_qspi_set_mode(struct udevice * bus,uint mode)383 static int tegra210_qspi_set_mode(struct udevice *bus, uint mode)
384 {
385 struct tegra210_qspi_priv *priv = dev_get_priv(bus);
386
387 priv->mode = mode;
388 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
389
390 return 0;
391 }
392
393 static const struct dm_spi_ops tegra210_qspi_ops = {
394 .claim_bus = tegra210_qspi_claim_bus,
395 .xfer = tegra210_qspi_xfer,
396 .set_speed = tegra210_qspi_set_speed,
397 .set_mode = tegra210_qspi_set_mode,
398 /*
399 * cs_info is not needed, since we require all chip selects to be
400 * in the device tree explicitly
401 */
402 };
403
404 static const struct udevice_id tegra210_qspi_ids[] = {
405 { .compatible = "nvidia,tegra210-qspi" },
406 { }
407 };
408
409 U_BOOT_DRIVER(tegra210_qspi) = {
410 .name = "tegra210-qspi",
411 .id = UCLASS_SPI,
412 .of_match = tegra210_qspi_ids,
413 .ops = &tegra210_qspi_ops,
414 .ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata,
415 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
416 .priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv),
417 .per_child_auto_alloc_size = sizeof(struct spi_slave),
418 .probe = tegra210_qspi_probe,
419 };
420