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Searched refs:QIXIS_PWR_CTL2 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/common/
H A Darm_sleep.c81 tmp = in_8(qixis_base + QIXIS_PWR_CTL2); in ls1_psci_resume_fixup()
83 out_8(qixis_base + QIXIS_PWR_CTL2, tmp); in ls1_psci_resume_fixup()
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dls102xa_psci.c182 tmp = in_8(qixis_base + QIXIS_PWR_CTL2); in ls1_deep_sleep()
184 out_8(qixis_base + QIXIS_PWR_CTL2, tmp); in ls1_deep_sleep()
/openbmc/u-boot/include/configs/
H A Dls1021aqds.h230 #define QIXIS_PWR_CTL2 0x21 macro