Searched refs:QE_PIO_PINS (Results 1 – 3 of 3) sorted by relevance
66 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? in __par_io_config_pin()71 pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS - in __par_io_config_pin()72 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()75 new_mask2bits = (u32) (dir << (QE_PIO_PINS - in __par_io_config_pin()76 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()79 if (pin > (QE_PIO_PINS / 2) - 1) { in __par_io_config_pin()89 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? in __par_io_config_pin()94 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()96 if (pin > (QE_PIO_PINS / 2) - 1) { in __par_io_config_pin()126 if (pin >= QE_PIO_PINS) in par_io_data_set()[all …]
55 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_get()66 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_set()96 qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i)); in qe_gpio_set_multiple()98 qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i)); in qe_gpio_set_multiple()241 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); in qe_pin_set_dedicated()242 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); in qe_pin_set_dedicated()243 bool second_reg = pin > (QE_PIO_PINS / 2) - 1; in qe_pin_set_dedicated()316 gc->ngpio = QE_PIO_PINS; in qe_add_gpiochips()
139 #define QE_PIO_PINS 32 macro